Bring up and debug the twosigma/frost RV32GCB SystemVerilog CPU (an out-of-order, Tomasulo-style core): the…

Bring up and debug the twosigma/frost RV32GCB SystemVerilog CPU (an out-of-order, Tomasulo-style core): the…: a task in Long-Horizon Terminal-Bench (LHTB) (Harbor dataset). You are the verification engineer bringing up the frost RV32GCB RISC-V core (an out-of-order, Tomasulo-style superscalar…