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RTL Implementation Task: ADC Controller Sampling FSM

RTL Implementation Task: ADC Controller Sampling FSM: a task in TitanBench: A Benchmark for Agentic RTL Design and Verification (Harbor dataset). Implement rtl/adc ctrl fsm.sv — the sampling state machine for OpenTitan's ADC controller.

The task

Implement `rtl/adc_ctrl_fsm.sv` — the sampling state machine for OpenTitan's ADC controller.

Part of billshockley/titanbench.