billshockley/titanbench
TitanBench: A Benchmark for Agentic RTL Design and Verification: Harbor dataset on Hugging Face with 108 tasks. See what each task asks, how it is graded and what it runs in, then run an agent on it.
Tasks
- RTL Implementation Task: ADC Controller Core
- RTL Implementation Task: ADC Controller Sampling FSM
- RTL Implementation Task: ADC Controller Interrupt Module
- RTL Implementation Task: ADC Controller Full IP
- RTL Implementation Task: AES Cipher Control
- RTL Implementation Task: AES Cipher Core
- RTL Implementation Task: AES Main Control
- RTL Implementation Task: AES Core Integration
- RTL Implementation Task: AES CTR Mode
- RTL Implementation Task: AES Key Expand
- RTL Implementation Task: AES MixColumns
- RTL Implementation Task: AES PRNG Clearing
- RTL Implementation Task: AES Full IP
- RTL Implementation Task: AES S-Box + SubBytes
- RTL Implementation Task: AES ShiftRows + SelBufChk
- RTL Implementation Task: Alert Handler Accu
- RTL Implementation Task: Alert Handler Class
- RTL Implementation Task: Alert Handler Esc-timer
- RTL Implementation Task: Alert Handler Lpg-ctrl
- RTL Implementation Task: Alert Handler Ping-timer
- RTL Implementation Task: Alert Handler Full IP
- RTL Implementation Task: AON Timer
- RTL Implementation Task: CSRNG — Block Encrypt
- RTL Implementation Task: CSRNG — Command Stage
- RTL Implementation Task: CSRNG — Core Integration
- RTL Implementation Task: CSRNG — CTR DRBG
- RTL Implementation Task: CSRNG — Main State Machine
- RTL Implementation Task: CSRNG Full IP
- RTL Implementation Task: CSRNG — State Database
- RTL Implementation Task: OpenTitan DMA Controller
- RTL Implementation Task: OpenTitan GPIO
- RTL Implementation Task: HMAC Core
- RTL Implementation Task: HMAC / SHA-2
- RTL Implementation Task: I2C Bus Monitor
- RTL Implementation Task: I2C Controller FSM
- RTL Implementation Task: I2C Core Integration
- RTL Implementation Task: I2C FIFO-SRAM Adapter
- RTL Implementation Task: I2C FIFO Management
- RTL Implementation Task: I2C Full IP
- RTL Implementation Task: I2C Target FSM
- RTL Implementation Task: keymgr Control FSM
- RTL Implementation Task: Key Manager Error Collection ( keymgr err )
- RTL Implementation Task: Key Manager KMAC Interface ( keymgr kmac if )
- RTL Implementation Task: Key Manager Full IP
- RTL Implementation Task: keymgr Sideload Key Controller
- RTL Implementation Task: RV TIMER Core
- RTL Implementation Task: RV TIMER Full IP
- RTL Implementation Task: SRAM Controller — Alert & Escalation
- RTL Implementation Task: SRAM Controller — HW Initialization
- RTL Implementation Task: SRAM Controller — Scrambling Key Request
- RTL Implementation Task: SRAM Controller
- RTL Implementation Task: SRAM Controller — SRAM Access Path
- RTL Implementation Task: UART Full IP
- RTL Implementation Task: USB Full-Speed PHY (TX + RX)
- RTL Implementation Task: USB Full-Speed Receiver
- RTL Implementation Task: USB Full-Speed Transmitter
- RTL Implementation Task: USBDEV Full IP
- RTL Implementation Task: OpenTitan USB Device Link-State FSM
- ADC CTRL: clock gating
- ADC CTRL: filters both
- ADC CTRL: filters interrupt
- ADC CTRL: filters interrupt fixed
- AES: core fi
- AES: gcm save restore
- AES: nist vectors
- AES: nist vectors gcm
- AES: readability
- AES: reseed
- ALERT HANDLER: entropy stress
- ALERT HANDLER: esc alert accum
- ALERT HANDLER: random classes
- AON TIMER: alternating enable on off
- AON TIMER: jump
- AON TIMER: wkup count cdc hi
- CSRNG: alert
- CSRNG: intr
- DMA: abort
- DMA: config lock
- DMA: memory region lock
- DMA: stress all
- GPIO: filter stress
- GPIO: full random
- GPIO: intr with filter rand intr event
- GPIO: random long reg writes reg reads
- HMAC: burst wr
- HMAC: error
- HMAC: stress reset
- I2C: host fifo reset rx
- I2C: host may nack
- I2C: host perf
- I2C: host perf precise
- I2C: host smoke
- KEYMGR: cfgen during op
- KEYMGR: kmac error response
- KEYMGR: lc disable
- KEYMGR: sideload protect
- KEYMGR: stress all
- RV TIMER: cfg update on fly
- RV TIMER: disabled
- SRAM CTRL: executable
- SRAM CTRL: lc escalation
- SRAM CTRL: regwen
- UART: intr
- UART: loopback
- UART: rx start bit filter
- UART: tx ovrd
- USBDEV: invalid sync
- USBDEV: spurious pids ignored