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RTL Implementation Task: ADC Controller Interrupt Module

RTL Implementation Task: ADC Controller Interrupt Module: a task in TitanBench: A Benchmark for Agentic RTL Design and Verification (Harbor dataset). Implement rtl/adc ctrl intr.sv — the interrupt aggregation and AON→core-clock CDC module for OpenTitan's ADC controller.

The task

Implement `rtl/adc_ctrl_intr.sv` — the interrupt aggregation and AON→core-clock CDC module for OpenTitan's ADC controller.

Part of billshockley/titanbench.