HF RL Explorer

RTL Implementation Task: HMAC Core

RTL Implementation Task: HMAC Core: a task in TitanBench: A Benchmark for Agentic RTL Design and Verification (Harbor dataset). You are working in /home/dev/workspace/code/ . Implement rtl/hmac core.sv . All other modules — rtl/hmac.sv (top), rtl/hmac reg top.sv (auto-generated register file), and…

The task

You are working in `/home/dev/workspace/code/`. Implement `rtl/hmac_core.sv`. All other modules — `rtl/hmac.sv` (top), `rtl/hmac_reg_top.sv` (auto-generated register file), and the `prim_sha2_32` SHA engine primitive — are pre-implemented and must not be modified.

Part of billshockley/titanbench.