RTL Implementation Task: UART Full IP
RTL Implementation Task: UART Full IP: a task in TitanBench: A Benchmark for Agentic RTL Design and Verification (Harbor dataset). The following are boilerplate and must not be modified : - rtl/uart.sv — top-level wrapper (TL-UL register interface, alerts) - rtl/uart reg top.sv — auto-generated…
The task
The following are boilerplate and **must not be modified**: - `rtl/uart.sv` — top-level wrapper (TL-UL register interface, alerts) - `rtl/uart_reg_top.sv` — auto-generated register interface - `pkg/uart_reg_pkg.sv` — register types (note: `TxFifoDepth=32`, `RxFifoDepth=64`)
Part of billshockley/titanbench.