HF RL Explorer

ADC CTRL: clock gating

ADC CTRL: clock gating: a task in TitanBench: A Benchmark for Agentic RTL Design and Verification (Harbor dataset). Verify filter wakeup and interrupts function correctly when fast clock is turned off as would occur in the system. Configure DUT with randomized filter parameters, filters, interrupt…

The task

> Verify filter wakeup and interrupts function correctly when fast clock is turned off as would occur in the system. Configure DUT with randomized filter parameters, filters, interrupt and wakeup enabled, low power sampling mode. Turn off fast clock, generate ADC data stream, and when wakeup occurs after a further…

Part of billshockley/titanbench.